22-26 May 2017 | Limassol | Cyprus
Embedded Tutorial 1
Title: Counteracting Malicious Faults in Cryptographic Circuits
Presenters: Ilia POLIAN (University of Passau – Germany) Francesco REGAZONI (ALaRI Institute, University of Lugano – Switzerland)
Tutorial Summary: In the area of testing, faults represent defects that occur during circuit manufacturing, or transient disturbances due to radiation or noise. This tutorial will focus on faults that an attacker deliberately injects into a security-critical circuit. We will explain the threats posed by fault-injection attacks, pointing out similarities and differences between “natural” and malicious faults, and detection methods and countermeasures applicable in both cases. We will describe various methods of malicious fault injection with high and low precision and discuss the necessary equipment (including commercially available solutions), as well as potential impact of such faults to system security. In particular, we will discuss the relationship of fault-injection attacks with other attack vectors and with test and measurement techniques.
Biography of Ilia POLIAN: Ilia Polian is a Full Professor and Chair of Computer Engineering at the University of Passau, Germany. He is active in the areas of test, hardware security and emerging architectures and published more than 100 articles within the last 10 years. This includes several works on fault-injection attacks and countermeasures, and he currently is a PI in an interdisciplinary DFG-funded projects on a specific class of such threats, called algebraic fault attacks. He received two Best Paper Awards (including ETS’14) and several further recognitions, and was involved in organization of ETS and a number of further leading scientific conferences. He is a senior member of the IEEE.
Biography of Francesco REGAZONI: Dr. Francesco Regazzoni is a postdoctoral researcher at the ALaRI Institute of University of Lugano (Lugano, Switzerland). He received his Master of Science degree from Politecnico di Milano and his PhD degree at the ALaRI Institute of University of Lugano. He has been assistant researcher at the Université Catholique de Louvain and at Technical University of Delft, and visiting researcher at several institutions, including NEC Labs America, Ruhr University of Bochum, EPFL, and NTU Singapore. His research interests are mainly focused on embedded systems security, covering in particular side channel attacks, electronic design automation for security, hardware Trojans, and low energy cryptography. He has published more than 50 journal and conference papers in the area of security and design automation, (including CHES, DAC, DATE, and ASP-DAC) and has been in the technical program committed of top conferences of the area (including CHES, DATE, HOST, and COSADE). Francesco is the work package leader of the WP7 “Physical Attack Resistant Methodologies” of the EU funded Horizon2020 SAFEcrypto project in the area of Post Quantum Cryptography. He worked extensively on fault attacks on cryptographic devices and software-level countermeasures.
Embedded Tutorial 2
Title: Security and Trust in the Analog/Mixed-Signal/RF Domain: A Survey and a Perspective
Presenter: Yiorgos MAKRIS (UT Dallas – USA)
Tutorial Summary: The objective of this tutorial is to summarize and present the available body of knowledge in trusted and secure design of analog/mixed-signal/RF ICs/IPs, covering both known vulnerabilities and available remedies. A comprehensive survey of the relevant literature will be provided, organized around four themes: (i) hardware Trojans and Trojan states in analog/mixed-signal/RF ICs along with existing detection/prevention methods, (ii) analog/mixed-signal/RF IP piracy scenarios and techniques for proving authenticity and ownership, (iii) analog/mixed-signal/RF IC counterfeiting and detection mechanisms, and (iv) limitations of existing methods in the analog/mixed-signal and RF domain, focusing on the gaps that exist in our current understanding of this problem and potential directions towards filing them and mitigating the threats in analog/mixed-signal/RF ICs/IPs.
Biography of Yiorgos MAKRIS: Prof. Makris received the Diploma degree in computer engineering and informatics from the University of Patras, Patras, Greece, in 1995, and the M.S. and Ph.D. degrees in computer science and engineering from the University of California at San Diego, La Jolla, CA, USA, in 1998 and 2001, respectively. After spending over a decade on the faculty of Electrical Engineering and of Computer Science at Yale University, he joined the University of Texas at Dallas, where he is currently a Professor of Electrical Engineering, leading the Trusted and Reliable Architectures (TRELA) Research Laboratory. His current research focuses on the applications of machine learning and statistical analysis in the development of trusted and reliable integrated circuits and systems, with particular emphasis in the analog/RF domain, and has been supported by NSF, SRC, ARO, DARPA, SRC, Boeing, Intel, LSI, IBM, and Texas Instruments. Prof. Makris serves as an Associate Editor of the IEEE Transactions on Information Forensics and Security, the IEEE Design and Test Periodical and the Springer Journal of Electronic Testing Theory and Applications, and served as a Guest Editor of the IEEE Transactions on Computers and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He also served as the General Chair (2016) as well as the Program Chair (2013-2014) of the IEEE VLSI Test Symposium, and as the Program Chair (2010-2012) of the Test Technology Educational Program (TTEP) of the IEEE Computer Society Test Technology Technical Council (TTTC). He also serves regularly as a Topic Coordinator and/or Program Committee Member for several IEEE and ACM conferences in the areas of VLSI Testing, Hardware Security, and Design Automation. Prof. Makris was the recipient of the 2006 Sheffield Distinguished Teaching Award, as well as Best Paper Awards from the 2013 Design Automation and Test in Europe Conference and the 2015 IEEE VLSI Test Symposium.
Embedded Tutorial 3
Title: Volume Diagnosis Data Mining
Presenter: Wu-Tung CHENG (Mentor Graphics – USA)
Tutorial Summary: This tutorial will present the basic concept of machine learning and data mining techniques. The focus is on the application of these techniques to identify the root causes of volume diagnosis scan test failure data. It will cover how to select proper machine learning features and parameters to support industrial usage. It also covers techniques used to avoid over-fitting caused by limited data and the noises of industrial scan failure diagnosis data. The identified root causes information not only can be used to improve yield analysis but also can reduce PFA cost by focusing on systematic defect failing die.
Biography of Wu-Tung CHENG: Wu-Tung Cheng is a Chief Scientist and Advanced Test Research Director in Mentor Graphics. He is an IEEE fellow since year 2000. He has over 150 publications and 57 patents in semiconductor manufacture test and diagnosis area. He received 2006 ITC best paper award, 2008 ITC honorable mention award, 2014 ATS best paper award. He received his Ph.D. degree in Computer Science from the University of Illinois at Urbana-Champaign in 1985.
Embedded Tutorial 4
Title: Challenges and Emerging Solutions in Testing Embedded IO interfaces in 2.5D and 3D Systems
Presenter: Salem ABDENNADHER (Intel – USA)
Tutorial Summary: With advances in VLSI technology, process, packaging and architecture, SoC systems continue to increase in complexity. This has resulted in an unprecedented increase in design errors, manufacturing flaws and customer returns in modern VLSI systems related to High Speed IO circuits. The situation will be exacerbated in future systems with smaller form factors, higher integration complexity, embedded IO’s, and more complex manufacturing process. Systems using embedded DRAM interconnected via a high density substrate with interposer-like technologies or via Thru-Silicon Via (TSV) are being introduced in a broad array of products. In this embedded tutorial we present testability methodology practices for 2.5D and 3D products with embedded IO interfaces. As opposed to conventional testing, 2.5D and 3D ICs test flows are more complex and new DFx methodologies will be presented that provide good coverage and visibility to isolate failures in High Volume Manufacturing.
Biography of Salem ABDENNADHER: Salem Abdennadher, Principal Technologist, Intel Corporation has 20 years of experience in mixed-signal design and DFT. Soon after graduating from Oregon State University 1992, he joined the industry and has worked with a research lab in France, Motorola, Level One Communications, and Intel. His recent publications and international patent filing in mixed signal DFT/BIST ranges from Filter BIST, On-chip Jitter BIST, to mixed signal behavioral modeling and noise extraction and prediction. Salem also has presented multiple tutorials through TTTC’s Test Technology Educational Program (TTEP) at ATS’04, LATW’05, VTS’05, ITC’05, ITC’06, DATE’07, ETS’07, ITC’08, ITC’09, VTS’09, ITC’10, ITC’11, DTIS 2012, ITC’15, ITC’16, and was an invited speaker for the ATS’05 and VTS’2016 industry challenges section.